1. Technical Field
The present invention relates to a test apparatus and a test method. In particular, the present invention relates to a test apparatus and a test method for detecting abnormalities in reading or writing of data from or to a memory under test.
2. Related Art
Recently, non-volatile memories such as a NAND flash memory have become widely used. The test apparatus for a memory device logically compares an output of the memory under test to an expected value, and judges the memory to be acceptable if the values match and to be defective if the values do not match. However, judging the memory to be defective merely because of a very slight discrepancy between the output and the expected value greatly decreases the yield of the memory device. Therefore, the memory device is provided in advance with backup storage regions that are used in place of storage regions in which a defect is detected. Furthermore, data can be corrected using error correction code (ECC) which allows for the presence of a small number of errors. In this way, even a memory device judged to be defective during testing may be acceptable if the detected errors are within an allowable range.
Such a test apparatus and test method for a memory device are shown in Japanese Patent Application Publication No. 2001-319493.
A conventional test apparatus manages errors in an acceptable memory device by detecting what types of errors occur in each block of the memory device. After detecting the types of errors, the test apparatus determines what following processes should be applied, such as a repair process that exchanges the defective blocks for backup blocks. However, there are many different types of errors, so storing all possible error types in the test apparatus greatly increases the necessary storage capacity for error storage, thereby increasing the scale of the test apparatus. Furthermore, all of the stored error information is not necessarily used in the following processes, and so the storage regions are not used efficiently.